Fast Page Mode DRAMs are among the most popular integrated circuit memory devices in use today. In fast page mode operation, a row address strobe (/RAS) is used to latch a row address portion of a multiplexed DRAM address. Multiple occurrences of the column address strobe (/CAS) are then each used to latch a new column address to access data within the selected row at the specified column location. Fast Page Mode DRAMs are said to be "Random Access" memory devices because a new address can be specified for each access cycle in a random order within an open page or row. In a read access, the falling edge of /CAS is used to latch a column address and to enable the DRAM outputs to drive selected data from the DRAM. When /CAS transitions high the DRAM outputs are placed in a high impedance state (tristate). As cycle times shorten, the period of time that data is valid at the outputs of a Fast Page Mode DRAM limits the usefulness of this mode of operation. For example, if the data valid time from /CAS precharge (tCPA) is thirty five nanoseconds, the minimum /CAS cycle time tPC is thirty five nanoseconds and the minimum /CAS high to data invalid time tOFF is three nanoseconds, then data is only guaranteed to be valid for three nanoseconds per cycle when operating at a maximum /CAS frequency of twenty eight megahertz.
Numerous alternatives to the standard DRAM architecture have been proposed in an effort to attain higher frequency data access cycles. Extended Data Out (EDO) DRAMs provide a longer period of time when data is valid at the outputs of a DRAM in a page mode cycle. In an EDO DRAM the data lines are not tristated between read cycles in a page mode operation. Instead, data is held valid after /CAS goes high until sometime after the next /CAS low transition occurs, or until /RAS or the output enable (/OE) goes high. By providing a wider data valid time window, the device cycle times can be decreased. Determining when valid data will arrive at the outputs of a fast page mode or EDO DRAM can be a complex function of when the column address inputs are valid, when /CAS falls, the state of /OE and when /CAS rose in the previous cycle. The period during which data is valid with respect to the control line signals (especially /CAS) is determined by the specific implementation of the EDO mode, as adopted by the various DRAM manufacturers.
Other methods to shorten memory access cycles tend to require additional circuitry, additional control pins and nonstandard device pinouts. The proposed industry standard synchronous DRAM (SDRAM) for example, in addition to /RAS, /CAS, /WE and /CS, has an additional pin for receiving a system clock signal. SDRAMs also have a clock enable pin, a bank address and a data mask pin. Also, the /RAS, /CAS, /WE and /CS signals of a SDRAM have dramatically different timing requirements and perform different functions than signals with similar names which are found on page mode DRAMs. The addition of several control pins has required a deviation in device pinout from standard DRAMs which further complicates design efforts to utilize these new devices. Significant amounts of additional circuitry are required in the SDRAM devices which in turn result in higher device manufacturing costs.